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Old fab…or new fabulous

How to use an outdated fab to produce 5G and sub-25nm CMOS-equivalent chips, remove the risks associated with Neon gas supply and delay the need for Extreme UV (EUV)


 SFN (Search for the Next) set out to transform the entire electronics industry by going back to where semiconductors began and taking a fresh look at the physics. A new transistor technology, Bizen, effectively gives industry a time-machine breathing new life into old fabs, massively increasing profitability and slashing CAPEX

Yet it is well-documented that there is a global semiconductor shortage which must be addressed, as well as Europe’s (and the USA’s) over-reliance on a tiny number – less than ten companies – that make at least 70% of the world’s chips and around 90% of the world’s complex semiconductors. To make the point even clearer, in a UK government report (2) dated 2 July 2021, the Rt Hon Oliver Dowden (then Secretary of State for Digital, Culture, Media and Sport) stated: “It is vital that we position ourselves for future generations of technology, particularly 5G, by ensuring that secure, diverse and resilient supply chains underpin our critical national infrastructure”. However, the semiconductors that are required to enable 5G telecoms systems require 25nm manufacturing in order to meet the required performance levels. This is not state-of-the-art: that would be 5nm or even 3nm. However, the finest geometry fabs that still exist in the UK are at 180nm.

To build, equip and bring online even a 25nm fab would take several billion dollars and take 3-5 years. During which time, the UK (and anywhere else without at least 25nm fabrication capabilities) would be totally reliant on a handful of suppliers, primarily in Asia (Taiwan, Korea).

The EU has responded with the announcement in February 2022 by European Commission President Ursula von der Leyen of the European Chips Act (3). The aim of the act is to ‘mobilise more than €43 billion euros of public and private investments … [which] will ensure that the EU has the necessary tools, skills and technological capabilities to become a leader in [complex IC manufacture] … to secure its supply of semiconductors and to reduce its dependencies.’ Given the existing precarious position, it’s an ambitious plan - but it will also take eight years to reach its goal, even assuming the project remains on track. It is not clear what device geometry is being targeted. Also, from a UK perspective, since Brexit, the UK is unlikely to be included.

And there is another issue; any semiconductor plant that produces devices made at manufacturing nodes significantly under 500nm requires a steady supply of neon gas for the excimer laser sources that are used in the main equipment performing the photolithography process. To a great extent, the world’s neon gas supply is now either controlled by Russia or offline (Ukraine plants have been closed or destroyed since the invasion) (4). Advanced chip makers have been stockpiling neon since the 2014 Russian invasion of the Crimea, but stocks will run out quickly and it is expensive and time-consuming to build replacement neon gas plants.

In addition, when it comes to EUV lithography, ASML is the only supplier for the photolithography exposure equipment – yet another choke point in complex IC manufacture.

Another way

There is another way. A UK company, Search for the Next (SFN) has developed a new transistor structure (transistors being the basic element that make up semiconductor chips): the Zpolar® Transistor built using the Bizen® wafer process. A more detailed discussion of Bizen and the Zpolar transistor will be released later. Using the Zpolar transistor and tunnel mechanics, SFN have developed Zpolar Tunnel Logic (ZTL), a replacement for CMOS logic, which has increased performance (frequency per Watt) by 10 times, slashed manufacturing time by 50%, reduced the number of chip patterning layers required (hence cutting costs) and reduced overall die size (transistor plus interconnect) by 30x.

This combination of factors means that outdated semiconductor plants running at geometries of 180nm and even greater, which using CMOS are not suitable for advanced microprocessor and 5G communications chips, could immediately be brought back into play by simply running the Bizen process technology. The process would need to be ported to an existing facility – say Newport Wafer Fab in Wales. This would take three to four wafer runs of three to four weeks each to be run, tested and calibrated. No new equipment is required. No $5 billion (USD, est.)  factory.

3D Cone Diagram PORPDKLIB 500

Above is a graphical representation of the Bizen 'infrastructure time machine': the technology can operate horizontally ‘x’ across all markets, vertically ‘y’  through the segments, re-enable industry ‘z’, impacting everything through time since the creation of MOS ‘t’. To accomplish the design of the new transistor and tunnel mechanics, all segments of the industry, from the very physics foundation up, required a polar opposite ethos: moving from the designers dream to a manufactures dream of risk, cost, time, and resources. The graphic shows:

  • The foundation POR is the Bizen ‘Process of Reference’ for the wafer process with tunnel mechanics, every step owned, patented and unique to SFN.
  • The PDK are the Bizen devices ‘Process Development Kit’ including the Zpolar Transistor and tunnels, patented and unique to SFN.
  • The LIB are the Bizen cell ‘libraries’ including the Zpolar Tunnel Logic (ZTL) family, patented and unique to SFN.
  • $$$$$ from end products

The figure below shows how ZTL with a Bizen process compares to CMOS


area chart vs geometry

The horizontal axis shows the state of the art processing nodes getting smaller over the last quarter century. On the vertical axis, the purple text shows the benefits of Bizen Zpolar Tunnel Logic (ZTL) expressed as a CMOS geometry equivalence. So, for example, a ZTL IC made on a 500nm Bizen process will result in a chip that runs at the same clock speed, is the same size and delivers the same performance as the equivalent IC produced using 90nm CMOS. But there is more. ZTL does not suffer from the same ‘shoot-through’ behaviour that limits the speed of CMOS. ZTL has a completely linear speed relationship with power, so theoretically there is no limit to the clock speed. Therefore it would be possible to take that 500nm chip and increase the clock speed beyond what 90nm CMOS is capable of.  The green text shows the 500nm ZTL chip will run at a speed and performance equivalent to 13nm CMOS. The physical area of the 500nm ZTL IC will be larger than a 13nm CMOS chip, but it would also be significantly cheaper.

Therefore, although a 180nm FAB running the Bizen ZTL process would be ideal for a 5G application giving a CMOS equivalent of 25nm and huge cost savings, if there was a neon supply challenge, 500nm ZTL could be used to produce working 5G chips (or other complex, high speed CPUs), without the need for extremely high resolution laser photolithography machines.


The tables below compare KPIs of converting a fab from CMOS to Bizen.


The figures below shows the financial considerations. If we consider an old fab, such as Newport, now running the 180nm ZTL process (remember this results in an equivalence of 25nm CMOS but at zero extra cost), versus an unchanged situation where the fab is still running 180nm CMOS, there is a huge advantage to be gained in terms of net profit and value add. Furthermore, upgrading the 180nm CMOS fab to a 25nm fab has huge disadvantages in terms of upgrade cost and lost opportunity cost due to the time required for the upgrade to 25nm (upgrading to 25nm CMOS will take 60 months compared to 6 months for a 180nm ZTL upgrade).

(Bizen is orange, CMOS is blue.)




The global economy is much too dependent on foreign-owned and located semiconductor manufacturing. Current and proposed plans to build a leading-edge chip industry in Europe are too expensive and will take too long to implement, meaning that if and when they do come onstream, the dominant players today, such as TSMC and Samsung, will have already moved on by at least one if not two or more process nodes. We will be forever playing catch-up. Also, there is a supply risk to neon gas, one of the essential materials for advanced-node semiconductor manufacturing, and only a single source for photolithographic equipment needed at advanced nodes.

It is not new fabs that we need, it is new thinking. CMOS process technology – which has been used for 50 years – is no longer fit for purpose. ZTL (Zpolar Tunnel Logic) ICs offer die size, performance and manufacturing benefits on such a huge scale that existing fabs – here in the UK and elsewhere – can today, with no extra investment, be used to create high performance 5G and advanced CPUs. We are no longer dependant on a limited supplier base of neon gas. In addition, the performance of ZTL can match current state-of-the-art 4nm CMOS process by sacrificing die area and using a 180nm fab found in the UK, thus giving the further advantage of not needing extreme UV lithography for which ASML is the only supplier in the world.

Lastly, Bizen/ZTL will open a door to the possibility of a ten year old 28nm fab delivering sub-nanometre equivalent CMOS performance, which will push performance beyond the current limit of CMOS.

At a stroke, SFN is solving the three key issues that face the semiconductor industry today:

  • Bizen enables a 180nm fab to produce 5G and sub-25nm CMOS-equivalent chips
  • Bizen removes the risk associated with Neon gas supply
  • Bizen delays the need for Extreme UV required for sub 10nm CMOS devices, often called FinFETs at this geometry






Process Of Reference

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The process of reference ‘POR’ defines the physics of the Bizen wafer process.



Process Development Kit

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The process development kit, PDK, are the Bizen devices PDK including the Zpolar Transistor and tunnels.



Library Cells

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The Bizen cell libraries including the Zpolar Tunnel Logic (ZTL) family.